Wire Routing Congestion technical paper

The congestion of wires in the place and route (P&R) stage of chip design poses an increasingly significant challenge to creating low cost, high performance chip designs. High congestion requires an increased die size or more metal mask layers. Congestion also causes long wire routes that create new and unpredictable critical paths that affect signal integrity and timing closure.

Fixing wire routing congestion prior to the semiconductor physical design phase is essential.

This paper:

  • Presents trends in technology,
  • Introduces packet based network-on-chip as a means of enabling configuration link widths,
  • Shows experimental results, and
  • Describes other benefits of packet-based interconnect networks.

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