Failure modes, effects, and diagnostic analysis (FMEDA) for sophisticated chips with hundreds of IP blocks are fraught with complexity and opportunities for systematic errors. This presentation will describe an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics. The methodology scales with the size and complexity of an SoC and enables reuse for creating SoC platform derivative chips. This bottoms-up approach allows for increased automation and less FMEDA rework as the chip’s architecture is refined and changed during development. We will also discuss linkages to traceability.