Learn how to create more scalable and efficient cache coherent systems
As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions.
This white paper discusses the challenges and solutions in designing cache-coherent System-on-Chip (SoC) architectures, particularly in the increasing complexity of modern SoCs with diverse processing elements. It highlights the importance of cache coherency in maintaining data integrity across different cache levels. It introduces the Ncore™ cache coherent interconnect IP from Arteris as a solution for architects designing heterogeneous SoCs or chiplets. The paper explores the various types of coherency, including homogenous, heterogeneous, and I/O coherency, and addresses the complexities introduced by chiplets.
The following themes are explored:
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