Create more scalable heterogeneous cache coherent systems
As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions.
This white paper discusses the challenges and solutions in designing cache-coherent System-on-Chip (SoC) architectures, particularly in the increasing complexity of modern SoCs with diverse processing elements. It highlights the importance of cache coherency in maintaining data integrity across different cache levels. It introduces the Ncore™ cache coherent interconnect IP from Arteris as a solution for architects designing heterogeneous SoCs or chiplets. The paper explores the various types of coherency, including homogenous, heterogeneous, and I/O coherency, and addresses the complexities introduced by chiplets.
The following themes are explored:
- SoC Design Challenges: The paper outlines the growing challenges in SoC design, emphasizing the increasing complexity of multi-core processors, diverse processing elements, and the need for efficient communication between them. It illustrates the rise in SoC complexity over time.
- Types of Coherency: It provides insights into different types of cache coherency, including full homogenous, full heterogeneous, I/O coherency, and non-coherency, explaining their relevance in optimizing performance across diverse processing elements.
- Ncore Interconnect IP: The white paper introduces Ncore as a solution for cache-coherent SoC designs, detailing its benefits such as true heterogeneous cache coherency, scalability, and support for safety-critical applications. It also discusses Ncore's ISO 26262 certification for functional safety, ensuring its suitability for safety-critical SoC designs. The paper concludes by addressing the future trends in multi-die system design and how Ncore is positioned to meet these evolving requirements.
