Arteris Magillem Connectivity product is a design environment addressing complex SoC assembly challenges. It supports the IP-XACT standard for instantiating, configuring, and connecting IPs in SoC designs. System address maps, RTL netlists, and documentation can all be generated from one 'single source of truth' database. Magillem Connectivity ensures consistency, interoperability, and high system quality with a correct-by-construction methodology.


Powerful and intuitive design environment

Magillem Connectivity is the centerpiece of a powerful and intuitive single source of the truth design environment. It provides advanced functionalities to address the challenges of complex System-on-Chip (SoC) assembly within aggressive time-to-market constraints. The tool allows for the instantiation, configuration, and connection of IPs packaged according to the widely supported IP-XACT standard, enabling efficient SoC design.

Enhanced productivity and visibility

Magillem Connectivity offers various ways to create, edit, and review designs, including Tcl, Python, and Java scripting languages and a rich graphical user interface (GUI). It supports the generation of RTL netlists and other collateral data, such as makefile scripts for a wide range of EDA tools and connectivity reports. These capabilities provide clear visibility into the integration status of the design, improving productivity and enabling efficient collaboration among design teams.

Continuous integration and error reduction

Magillem Connectivity facilitates continuous integration with a robust automated SoC build process. This process can adapt to changing needs within a project, ensuring error-free connectivity and reducing cycle time to completion. The tool enables consistency and interoperability between different design flow steps, following a correct-by-construction methodology. This approach provides a high system quality by minimizing errors and ensuring the integrity of the design throughout the development process.

Download Now!