Implementing Low-Power AI SoCs Using NoC Interconnect Technology

Linley Spring Conference Presentation

Download this 15-slide presentation titled, "Implementing Low-Power AI SoCs Using NoC Interconnect Technology," presented by Matthew Mangan, Application Engineer of Arteris IP, at The Linley Group Spring Conference 2020.

As AI / ML processing systems have become more complex with the growing number and complexity of hardware accelerators, it has become increasingly difficult to optimize for both performance and power consumption. Resolving this conundrum is especially important for edge computing and automotive systems.This presentation describes lessons learned using network-on-chip (NoC) technology to implement AI processing SoCs that meet explosive bandwidth and tight latency requirements while meeting stringent power consumption needs.


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