Implementing Machine Learning and Neural Network Chip Architectures
Using Network-on-Chip Interconnect IP
Download this 17-slide presentation titled, "Implementing Machine Learning and Neural Network Chip Architectures," presented by Arteris CTO Ty Garibay.
Includes:
- Types processing elements for neural net acceleration
- Current state-of-the-art AI SoC architectures
- Influence of interconnect and memory architectures on AI data flow
