Download IEEE's "How to efficiently achieve ASIL-D compliance using NoC technology White Paper"

A closer look at ASIL-D compliance options for on-chip interconnects and NoCs, including redundancy, path diversity and error correction codes (ECC) is required to fully optimize an on-chip network to meet rapidly evolving technology and customer demands.

Compared with using path diversity and dynamic routing to handle failures in the NoC, Arteris’ functional safety approach to protecting the network with error correction and minimal replication has a number of clear advantages.

Learn why in the IEEE-produced paper!