AMS System-Level Verification and Validation using UVM in SystemC and SystemC AMS: Automotive Use Cases

This 12-page paper published in the peer-reviewed IEEE Design & Test journal explains how Universal Verification Methodology (UVM), initially developed for digital systems, can be extended to analog and mixed signal systems with the help if IP-XACT-based IP packaging and design flow automation.

Authors M. Barnasconi (NXP), K. Einwich (Fraunhofer), T. Vörtler (Fraunhofer), F. Pêcheux (LIP6), M.-M. Louërat (LIP6), J.P. Chaput (LIP6), Z. Wang (LIP6), P. Cuenot (Continental), I. Neumann (Continental), T. Nguyen (Infineon), R. Lucas (Arteris IP) and E. Vaumorin (Arteris IP) describe:

  • How UVM can be used for the simulation-based verification of a complex mixed-signal design
  • How UVM can be used on a Hardware In the Loop (HIL) system to verify/validate a FPGA prototype
  • How IP-XACT enables interconnection of the DUT to the verification platform and automates verification sequences

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