Arteris CodaCache Last-Level Cache (LLC) IP, is a configurable, standalone cache designed to enhance system performance, data locality, scalability, power efficiency, and cost-effectiveness in system-on-chip (SoC) designs. It aims to optimize data sharing among computing engines, accelerators, and data processing blocks by improving prefetching mechanisms to lessen reliance on main memory, thereby enhancing overall SoC performance. The cache is a shared resource, reducing memory access latency and power consumption by storing frequently accessed data closer to the processor cores. The CodaCache IP supports up to 8MB per AXI port, configurable associativity, cache flushing, ECC protection. CodaCache also supports a Functional Safety (FuSa) Option that meets ISO 26262 ASIL B and D standards, making it a critical element for SoC designs in various applications like high-performance computing, AI, and embedded systems.
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