Download CodaCache Datasheet

Arteris CodaCache Last-Level Cache (LLC) IP, is a configurable, standalone cache designed to enhance system performance, data locality, scalability, power efficiency, and cost-effectiveness in system-on-chip (SoC) designs. It aims to optimize data sharing among computing engines, accelerators, and data processing blocks by improving prefetching mechanisms to lessen reliance on main memory, thereby enhancing overall SoC performance. The cache is a shared resource, reducing memory access latency and power consumption by storing frequently accessed data closer to the processor cores. The CodaCache IP supports up to 8MB per AXI port, configurable associativity, cache flushing, ECC protection. CodaCache also supports a Functional Safety (FuSa) Option that meets ISO 26262 ASIL B and D standards, making it a critical element for SoC designs in various applications like high-performance computing, AI, and embedded systems.

What you’ll learn:

• Performance Enhancement and Scalability: The CodaCache IP boosts system performance by reducing memory latency and is highly scalable and configurable to fit different SoC designs.
• Power Efficiency and System Responsiveness: By reducing the frequency of memory accesses, it contributes to power efficiency and enhances system responsiveness.
• Reliability and Safety Compliance: Incorporates error detection and correction mechanisms like ECC and meets ISO 26262 standards for functional safety in automotive applications.