Tiled Approach to System Scaling

By Guillaume Boillet

At Chiplet Summit 2024, Arteris presented how NoC interconnect IP solutions help enable the chiplet ecosystem, learn more here. This year Arteris focused on how chip designers of AI accelerators can most effectively deliver large-scale meshed and tiled systems spanning across chiplet boundaries. Get a copy of this presentation on Tiled Approach to System Scaling.

What You'll Learn:

• Why large-scale SoCs deploy regular repeating arrays of processor elements.
• Why the geometry of the on-chip NoC interconnect should mirror the physical floorplan.
• Why the principle of tile-based scaling maps effectively to future multi-die solutions.