Building Better IP with RTL Architect NoC IP Physical Exploration by Arteris
By Arteris Shivakumar Musini and Frank Schirrmeister
Download this 30-slide presentation titled, "A Building Better IP with RTL Architect," presented by Arteris Principal Physical Design Hardware Engineer Shivakumar Musini and VP Solutions & Business Development Frank Schirrmeister as an award-winning presentation at SNUG Silicon Vally 2023.
- Overview of challenges with traditional Network-on-Chip (NoC) development
- Examples of faster physical exploration options with Synopsys RTL Architect
- Opportunities to improve the connection between the tools used for NoC architecture exploration and digital implementation for timing closure.