Accelerate AI SoC Designs with Arteris NoC Tiling

Arteris' latest network-on-chip (NoC) tiling innovation is revolutionizing AI and machine learning-enabled semiconductor designs. This emerging approach uses proven, robust network-on-chipIP to facilitate scaling, condense design time, speed testing and reduce design risk. It allowsSoC architects to create modular, scalable designs by replicating soft tiles across the chip. Eachsoft tile represents a self-contained functional unit, enabling faster integration, verification andoptimization.

Tiling coupled with mesh topologies within Arteris’ flagship NoC IP products, FlexNoC andNcore, are transformative for the ever-growing inclusion of AI compute into most SoCs. AI-enabled systems are growing in size and complexity yet can be quickly scaled with the additionof soft tiles without disrupting the entire SoC design. Together, the combination of tiling andmesh topologies provides a way to further reduce the auxiliary processing unit (XPU) sub-system design time and overall SoC connectivity execution time.

What you’ll discover:

• Scalable Performance: Easily scale your AI SoCs by 10X+ without changing the basicdesign, thanks to our mesh topology in FlexNoC and Ncore interconnect IP products.
• Power Reduction: Dynamically turn off NoC tiles to cut power consumption by 20% onaverage, making your AI applications more energy-efficient and sustainable.
• Dynamic Reuse: Reuse pre-tested NoC tiles to cut SoC integration time by up to 50%,accelerating your time-to-market.