The Ncore Multi-Die Option enables next-generation chiplet architectures by extending cache coherency beyond a single die. With support for UCIe 1.1, AMBA CHI/ACE, and advanced NUMA memory mapping, it delivers the low latency, high bandwidth, and unified system behavior required for rapidly scaling compute workloads.
Designed for both homogeneous scale-out and heterogeneous disaggregation, the Multi-Die Option maintains a consistent coherency domain while helping to reduce cost, improve yield, and enable optimal process-node specialization. With integrated automation and pre-verified PHY/controller support, it shortens design cycles and accelerates time to silicon.
Download the datasheet to learn how the Ncore Multi-Die Option helps you:
- Build scalable chiplet-based SoCs with coherency spanning 2–4 dies.
- Improve throughput with up to 256 GB/s per link and up to 4 links per die with optional link aggregation.
- Reduce latency using direct coherency message forwarding to remote dies.
- Enable homogeneous or heterogeneous chiplet architectures.
- Maintain a unified global address space using NUMA optimization.
- Simplify integration with pre-verified UCIe controller + PHY combinations.
- Ensure coherency across distributed Arm SMMUs with DVM propagation.
- Accelerate partitioning, configuration, and validation using Arteris tool flows.
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