Ncore Multi-Die Cache Coherent Interconnect IP Datasheet

Enable fast, scalable, and predictable cache coherency for modern multi-core and multi-die SoCs.

Ncore Mutli-Die is high-performance, multi-die cache-coherent interconnect IP designed to enable processors, accelerators, and chiplet-based compute clusters to share data quickly and consistently.

Supporting Arm AMBA CHI, ACE, and ACE-Lite protocols, Ncore Multi-Die delivers low-latency, high-bandwidth coherency across homogeneous and heterogeneous systems while maintaining predictable performance and system-level efficiency.

Built for scalability, Ncore Multi-Die supports directory-based coherency, advanced snoop filtering, and QoS-aware traffic management. Its modular architecture allows coherency to scale across CPU clusters, GPUs, DSPs, accelerators, and multi-die or chiplet-based systems.

The optional functional safety package is certified to ISO 26262 B and D for automotive applications and enables other safety-critical designs.

Download the datasheet to learn how Ncore Multi-Die helps you:

  • Ensure consistent shared memory: Maintain a coherent, low-latency view of shared data across heterogeneous processors and multiple chiplets using standards-based coherency protocols.
  • Scale across complex architectures: Extend coherency efficiently across large multi-core systems, heterogeneous compute clusters, and multi-die or chiplet-based designs.
  • Optimize performance and efficiency: Reduce unnecessary coherency traffic, improve bandwidth utilization, and manage power effectively without sacrificing system responsiveness.