FlexGen Multi-Die smart network-on-chip (NoC) IP is designed to automate the creation of high-performance NoC designs for multi-die, chiplet-based products. It leverages AI heuristics using machine-learning technology and decades of NoC IP expertise and incorporates physical and performance awareness to streamline the multi-die SoC design processes.
Automation within FlexGen Multi-Die facilitates the rapid creation and iteration of NoC topologies, providing engineers with a robust starting point for physical layout and synthesis. By automating critical tasks such as simulation, verification, and timing closure, FlexGen Multi-Die makes it easy to develop, verify and iterate non-cache-coherent, high-performance, low-power SoC interconnect configurations, whether on chip, or for chiplet-to-chiplet connections in multi-die products.
FlexGen Multi-Die makes NoC engineering expertise optional, enhancing productivity and allowing engineers to focus on innovation rather than manual interconnect adjustments. The IP supports essential industry-standard protocols and its functional safety (FuSa) option meets up to ASIL D requirements, making it suitable for safety-critical applications.
Download the data sheet to learn how FlexGen Multi-Die helps you with: