By Ashley Stevens
Chiplets are reshaping how advanced systems are architected, integrated, and scaled. As multi-die designs become mainstream in AI, high-performance computing (HPC), and automotive ADAS applications, new challenges emerge around IP packaging, die-to-die connectivity, and system-level interconnect decisions.
This presentation from Chiplet Summit 2026 explores whether an entire chiplet can be described, packaged, and reused using IP-XACT, and examines how die-to-die connectivity and interconnect architecture choices directly impact power, performance, area (PPA), and long-term scalability. It also addresses practical realities of chiplet-based design, including logical IP packaging and scalable multi-die system architectures.
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What You'll Learn:
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